New LDMOS Model Delivers Powerful Transistor Library— Part 1: The CMC Model

Introduction Non-linear transistor models are being increasingly utilized and demanded by the power amplifier design community because they provide access to multiple simulator capabilities, including DC analysis, as well as analyses of small-signal, nonlinear, time domain, and complex modulation effects. The availability of accurate, validated models eliminates the need for designers to make their own source and load pull and S-parameter measurements on every device, and allow fast “what-if” analysis e.g. change frequency band, drain voltage etc. Savvy semiconductor marketing departments are also recognizing that more and more design engineers use simulators to minimize design risk, reduce design spins and cut design time. Good models will ultimately sell more product. It is well recognized that excellent power performance and linearity can be achieved at low cost using laterally diffused metal-oxidesemiconductor (LDMOS) transistors. In fact they are the technology of choice for base station applications below a couple of GHz as well as many other RF and microwave applications. Existing LDMOS FET large-signal models show a number of disadvantages. They tend to show poor prediction of IMDs, do not work in the sub-threshold region, lack a dynamic self-heating effect, do not use closedform analytic equations to represent channel current, have complex extraction routines and do not scale well with the number of cells. Balancing the trade-off between linearity and efficiency and designing optimal matching and bias networks requires more accurate LDMOS models with better treatment of these effects. Moreover, increasingly complex digital modulation schemes are placing increased demands on model fidelity through 5th or 7th order distortion predictions. This paper describes a new model that meets this challenge in an elegant and robust way. Part 1 of this paper outlines the topology and methods used to extract and validate a This new LDMOS model accurately predicts both small-signal and nonlinear performance, and is scalable for devices of different sizes and power output capabilities